DRT: Thesis subject SL-DRT-18-0290
Future computers in high-performance and embedded systems lead to complex memory hierarchies. Hundreds of computing nodes will have to be connected to tera-bytes of memories. In such systems, both the processing units (CPU, GPU, DSP, FPGA) and the memories (DRAM, NVRAM,
FLASH) can be heterogeneous.
Several architectures exist (distributed memory, shared memory, NUMA) with different hardware implementations (cache coherence, communication protocols), software implementations (thread parallelism, OpenMP, transactions) and communication technologies between processing units and memory (MPI, RDMA, RoCE, CCIX, GenZ). None of the approaches above offer a simple, unified programming model and memory model for parallel applications.
The purpose of this Ph.D. Thesis is to study the possibility of using emerging technologies related to computing units, hybrid memories (persistent or not) and remote communication standards in order to accelerate data sharing onto heterogeneous platforms and provide a
convenient programming model.
Laboratoire Calcul Embarqué
Start date of the thesis: 01/10/2018
Sciences et Technologies de l'Information et de la Communication (STIC)
17 rue des Martyrs
38054 Grenoble Cedex 9